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17 Jan 2006 The transformation process increases processor performance by substantially increasing the instruction-level parallelism available during execution. This instruction stream is then written out to the instruction stream cache 104 in a format which is parallel and can note dependencies and other information
Many of these proposals such as VLIW, superscalar, and even relatively old ideas such as vector processing try to improve computer performance by exploiting instruction-level parallelism. They take advantage of this parallelism by issuing more than one instruction per cycle explicitly (as in VLIW or superscalar machines)
scheduling & VLIW. • How do we ensure we have ample instruction-level parallelism? • Branch prediction Most instruction streams do not have huge ILP so • this limits performance in a superscalar processor .. Note: must check for branch match now, since can't use wrong branch address. Branch PC. Predicted PC.
Note that this technique is independent of both pipelining and superscalar. Current implementations of out-of-order execution dynamically (i.e., while the program is executing and without any help from the compiler) extract ILP from ordinary programs. An alternative is to extract this parallelism at compile time and somehow
Instruction Level Parallelism. What is it? We have seen that with pipelining we can overlap the execution of instructions, thus executing multiple instructions in parallel. However, we also saw that the amount of parallelism can be limited by hazards in the pipeline. We can characterize the performance of the pipeline by the
Thread Level Parallelism. Advanced Computer Architecture — Hadassah College — Fall 2012. Summary of Superscalar Processing. IF. ID. Data. Memory. Instruction. Memory. Instruction. Pool. Reorder. Buffer. EX. Load. EX. Store. EX. Single CPU. Virtual registers and architectural registers prevent false dependencies.

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March 2018