From NHM processor onward, Intel processors can support hardware accelerated CRC32c algorithm with the new CRC32 instruction in SSE
12 Apr 2011 A fast and efficient method of computing a Cyclic Redundancy Check (CRC) on Intel processors for the fixed (degree-32) iSCSI polynomial, using the CRC32 instruction introduced in Intel Core i7 processors.
First of all the Intel's CRC32 instruction serves to calculate CRC-32C (that is uses a different polynomial that regular CRC32. Look at the Wikipedia CRC32 entry). To use Intel's hardware acceleration for CRC32C using gcc you can: Inline assembly language in C code via the asm statement; Use intrinsics

28 Feb 2012 Intel has recently introduced a new instruction, namely CRC32, to address a computational bottleneck in protocols such as ISCSI and RDMA that use CRC32C for data integrity checks. This instruction is designed to accumulate the CRC32C value of a buffer of arbitrary length, by a sequence of invocations
To incrementally accumulate a CRC32 value, software retains the result of the previous CRC32 operation in the destination operand, then executes the CRC32 instruction again with new input data in the source operand. Data contained in the source operand is processed in reflected bit order. This means that the most
4 Jun 2010 CRC32 instruction. CRC (Cyclic Redundancy Check) is a remainder from dividing your message by a polynomial.
It also added a CRC32 instruction to compute cyclic redundancy checks as used in certain data transfer protocols. These instructions were first implemented in the Nehalem-based Intel Core i7 product line and complete the SSE4 instruction set.
A Cyclic Redundancy Check (CRC) is the remainder, or residue (typically 32 bits), of binary division of a potentially long message, by a CRC polynomial [7]. This technique is ubiquitously employed in communication and storage applications due to its effectiveness at detecting errors.

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March 2018