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5 Apr 2007 there was only a single ARM Architecture Reference Manual, with document No part of this ARM Architecture Reference Manual may be.
28 Sep 2011 Cortex-A15 Technical Reference Manual. Preface About the Cortex-A15 processor . . Large Physical Address Extension architecture .
Instruction Set Attribute Register 0 The ID_ISAR0 characteristics are:Purpose Provides information about the instruction set that the processor supports. Usage
The processor implements VFPv4-D32. See the ARM Architecture Reference Manual for information on the VFPv4 instruction set. In the Cortex-A15 VFP
The ARM Cortex-A15 MPCore is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. . Jump up ^ "Cortex-A15 MPCore Technical Reference Manual"; Jump up Jump up ^ "Samsung Exynos 5 Dual (Exynos 5250) RISC Microprocessor User's Manual Revision 1.0" (PDF).
free, worldwide licence to use this ARM Architecture Reference Manual for the the ARM Architecture Reference Manual or any products based thereon.
Table 11.1 gives a summary of the Cortex-A15 PMU registers. Event Count Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R
Standard ARM Cortex-A15 MPCore processor Full ARMv7-A architecture instruction set. • 3-issue . A15 Technical Reference Manual (TRM) r2p2. – GIC-400
26 Apr 2011 ARM Cortex-A15 MPCore Technical Reference Manual,TRM. Program Flow Trace architecture · 1.3. Security Extensions architecture.

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February 2018