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In the domain of central processing unit (CPU) design, hazards are problems with the instruction pipeline in CPU microarchitectures when the next instruction cannot execute in the following clock cycle, and can potentially lead to incorrect computation results. Three common types of hazards are data hazards, structural
Data -- a data value is not available when/where it is needed. • Control -- the next instruction to execute is not known. • Two ways to deal with hazards. • Removal -- add hardware and/or complexity to work around the hazard so it does not exist. • Bypassing/forwarding. • Speculation. • Stall -- Sacrifice performance to prevent
4 Mar 2010 Pipelining doesn't help latency of single task, it helps throughput of entire workload. • Multiple tasks operating simultaneously using different resources. • Potential speedup = Number pipe stages. • Pipeline rate limited by slowest pipeline stage. • Unbalanced lengths of pipe stages reduces speedup.
Pipelining hazards. • Pipeline hazards prevent next instruction from executing during designated clock cycle. • There are 3 classes of hazards: – Structural Hazards: • Arise from resource conflicts. • HW cannot support all possible combinations of instructions. – Data Hazards: • Occur when given instruction depends on data
Pipeline 1. Hazards. Situations that prevent starting the next instruction in the next cycle. Structure hazards. – A required resource is busy. Data hazard. – Need to wait for previous instruction to complete its data read/write. Control hazard. Computer Organization II. Control hazard. – Deciding on control action depends on
If data is available elsewhere in the pipeline, there is no need to stall. • Detect condition. • Bypass (or forward) data directly to the consuming pipeline stage. • Bypass eliminates stalls for single-cycle operations. – reduces longest stall to N-1 cycles for N-cycle operations
4. Goals for Today. Data Hazards. • Data dependencies. • Problem, detection, and solutions. – (delaying, stalling, forwarding, bypass, etc). • Forwarding unit. • Hazard detection unit. Next time. • Control Hazards. What is the next instruction to execute if a branch is taken? Not taken?
28 Sep 2005 September 28, 2005. 6.823 L6- 10. Arvind. Resolving Data Hazards. Freeze earlier pipeline stages until the data becomes available ? interlocks. If data is available somewhere in the datapath provide a bypass to get it to the right stage. Speculate about the hazard resolution and kill the instruction later if
“Golden Handcuffs" of binary compatibility affect design 20 years later, as Moore predicted. • Not too difficult to make faster, as Intel has shown. • HP/Intel announcement of common future instruction set by 2000 means end of 80x86??? • “Beauty is in the eye of the beholder". – At 50M/year sold, it is a beautiful business
Structural Hazards are caused by conflicts in resource usage. • Data Hazards are caused by instructions that require results from a previous (uncompleted) instruction. • Control Hazards are caused by instructions that change the Program Counter.
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