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This processor implements "wait for interrupt" mode with a CP15 write as in ARMv5. On ARMv5 and ARMv6 processors, attempting to execute the WFI instruction will cause a undefined instruction exception to be taken. ARMv6K and ARMv6T2 include the WFI instruction, meaning that these processors do not cause an
The five versions of the ARM instruction set architecture to date are as follows: Version 1. This version was implemented only by ARM1, and was never used in a commercial product. It contained: • the basic data-processing instructions (not including multiplies). • byte, word, and multi-word load/store instructions.
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After execution of some CP14 or CP15 instructions, the processor natively performs a pipeline flush before it executes the next instructions. This control bit imposes a pipeline flush on CP14 and CP15 instructions that do not natively include one: 0 = does not impose a pipeline flush on CP14 or CP15 instructions, reset value.
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Writing c7 with a combination of CRm and an Opcode_2 not listed in Table 3.29 gives Unpredictable results. If Opcode_1 = 0, these instructions are applied to a level one cache system. All other Opcode_1 values are reserved. All CP15 c7 operations can only be performed in a privileged mode, except Data Synchronization
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